UNLOCK THE AIoT
Introducing xcore.ai – a fast and economical platform for the AIoT, which delivers on flexibility without sacrificing performance. Enjoy high performance AI, DSP, I/O and control in a single device.
Efficient data capture and processing with deep neural networks; inferencing and characterisation of 8bit, 16bit, 32bit and binarized network models are supported. Programmable in C with standard tools, and frameworks.
Fast and predictable, xcore.ai delivers high performance compute at the edge. DSP, AI, control and communication can be processed concurrently with execution determinism measured in single cycles.
Incredible processing power for the cost. With flexible forms of compute and connectivity in a single device, eBOM is kept low, enabling manufacturers to design intelligent products that make life simpler, safer and more satisfying for all.
STAND OUT PERFORMANCE
Architected to deliver high processing and low eBOM. Easy to use, cost effective and scalable. It’s designed for smart, connected products across multiple applications.
more 16-bit MAC
* performance compared with ARM Cortex M7 @ 600MHz
faster I/O processing
These tools, libraries and guides will help to bring your projects to life using the xcore.ai series.
|Part Number||Package||MIPS||Cores||Internal RAM||OTP memory||Temperature||IO voltage||IO||USB PHY||MIPI||External Memory||Status|
|60pin QFN (7x7mm)||2400||16||2 x 512KB||2 x 4KB||Commercial||1v8||34||1||No||No||Available September 2021 |
|60pin QFN (7x7mm)||2400||16||2 x 512KB||2 x 4KB||Commercial||3v3||34||1||No||No||Available September 2021|
|265pin FBGA (14x14mm)||2400||16||2 x 512KB||2 x 4KB||Commercial||1V8 / 3V3||128||1||Single or Dual lane MIPI D-PHY receiver||LPDDR1||Available September 2021|
|60pin QFN (7x7mm)||3200||16||2 x 512KB||2 x 4KB||Commercial||1v8||34||1||No||No||Contact XMOS|
|60pin QFN (7x7mm)||3200||16||2 x 512KB||2 x 4KB||Commercial||3v3||34||1||No||No||Contact XMOS|
|265pin FBGA (14x14mm)||3200||16||2 x 512KB||2 x 4KB||Commercial||1V8 / 3V3||128||1||Single or Dual lane MIPI D-PHY receiver||LPDDR1||Contact XMOS|
WHITEPAPER AND REPORTS
This project received funding from the European Union Horizon 2020 research and innovation programme under Grant Agreement No 849469.